Semiconductor devices are commonly formed by processing a relatively large flat wafer of semiconductor material to form chip regions including electronic circuits to be incorporated in a single chip. Each chip typically has contacts exposed at a front surface of the wafer and electrically connected to the circuit elements of the chip. To release individual chips, the wafer is severed along predefined saw lanes.
A chip is commonly provided with a chip package. The chip package provides environmental and mechanical protection to the chip and facilitates connectivity between the chip and external circuitry such as, for example, a printed circuit board or other external circuit panel. It has been proposed to fabricate the chip packages by providing, on the front surface of a wafer, some or all structures constituting the package before severing the substrate. This approach is commonly referred to as “wafer level” packaging of the chips.
A packaged chip commonly includes a dielectric structure and electrical terminals disposed on the dielectric structure and connected to contact pads of the chip. The terminals may be disposed at a greater spacing, or pitch, than the contact pads so that the packaged chip can be readily mounted on a circuit panel by solder-bonding the terminals to the corresponding contacts of a circuit panel. In some instances, the terminals may be movable to some extent relative to the body of the chip.
Moveable terminals can reduce stress in the solder bonds between the terminals and contacts of the circuit panel. Such stress may arise due to factors such as differences in thermal expansion or contraction of the chip and the circuit panel during the fabrication or service of the assembly.
It has been proposed to form compliant posts on the front surface of a wafer, and form metallic conductors leading from the contacts of the wafer, up the side walls of the posts to terminals disposed on the tips of the posts, and then sever the wafer to provide individual packaged chips. The compliance of the posts allows the terminals to move relative to the chip. In some cases, however, the traces extending on the side walls of the posts are susceptible to fatigue failure in service.
Despite considerable effort in the art heretofore devoted to development of wafer level chip packages and methods of fabricating such packages, further improvements would be desirable.